Author : Vijayalaxmi P 1
Date of Publication :6th June 2017
Abstract: Security is one of the most important features of industrial products. Cryptographic algorithms are mainly used for this purpose to obtain confidentiality and integrity of data in industry. One of the main concerns of researchers in designing cryptographic algorithms is efficiency in either soft- ware implementation or hardware implementation. However, the efficiency of some well-known algorithms is highly questionable. The main goal of this paper is to present a novel processor architecture called CIARP (stands for Crypto Instruction-Aware RISC Processor) being feasible for high speed implementation of low throughput cryptographic algorithms. CIARP has been designed based on a proposed instruction set named Crypto Specific Instruction Set (CSIS), that can speed up encryption and decryption processes of data.
Reference :
-
- D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3rd ed., Morgan Kaufmann, 2005.
- D. R. Gonzales, “Micro-RISC architecture for the wireless market,” IEEE Micro, pp. 30-37, July/August 1999.
- A. Kalambur and M. J. Irwin, “An extended addressing mode for low power,” In Proc. of the IEEE Symposium on Low Power Electronics,pp. 208-213, August 1997.
- S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, and A.Yoaz, “A Novel Renaming Scheme to Exploit Value Temporal Locality through Physical Register Reuse and Unification,” In Proc. of the 31st MICRO, pp. 216- 225, 1998.
- S. Balakrishnan and G.S. Sohi, “Exploiting Value Locality in Physical Register Files,” In Proc. of 36th MICRO, pp. 265-276, Dec 2003.
- J.-L. Cruz, A. Gonzalez,M. Valero, N.P. Tophanm, “Multiple-Banked Register File Architectures,” In Proc. of 27th ISCA, pp. 316-325, June 2000
- R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi, “Reducing the Complexity of the Register File in Dynamic Superscalar Processors,” In Proc. of 34th MICRO, pp. 237-248, Dec.2001.
- The SPARC Architecture Manual Version 8, SPARC International, Pren- tice Hall, 1992.
- I. Hashmi, H.M.H Babu, “An Efficient Design of a Reversible Barrel Shifter,” International Conference on VLSI design, pp. 93-98, jan. 2010. [10] Paul Gigliotti, “Implementing Barrel Shifters Using Multipliers,” Xilinx Corp. , August 17, 2004.
- K. Nakano, Y. Ito, “Processor, Assembler, and Compiler Design Edu- cation Using an FPGA,” IEEE International Conference on Parallel and Distributed Systems, pp. 723-728, Dec. 2008.
- M. Morris Mano, Computer System Architecture, Prentice-Hall, 1993.